#
# $Id: MCR3.GAM 1.4 1997/07/04 10:01:34 MCUDDY Exp $
# 
# File: mcr3.gam -- game configuration file for "MCR/III" systems
#

# ----------------------------------
# MCR/III cpu board
# ----------------------------------

HardwareType = "MCR"
DispClass = "SVGA"
TileRomInv = -1

MCR_TileBoard = "M3"
MCR_SprBoard = "M3"
CtrlScanAlways = 0

MCR_Portrait = 0

#include ssio.gam

# ------------------------------------------------------------------------
# common definitions for MCR cpu boards
# ------------------------------------------------------------------------

# this is tile memory.
#CRam = 0xF000 0x800
TileBase = 0xF000
TileMemLen = 0x800
TileAttrOff = 1
TileInc = 2

# program memory.
CRam = 0xE000 0x800
# ... and it's non-volatile
NVRam = 0xE000 0x800

# sprite memory
CRam = 0xE800 0x400
SprBase = 0xE800
SprSize = 0x200


# this is in I/O space...
ACmdRegOut = 0x1C 0x04
AStatIn = io 0x07

# start of Palette SRAM.
PalRam = 0xF800
PalRamLen = 0x100

# CpuReadIoFF = 0x00 2
# CpuReadIoFF = 0x10 1
# CpuReadIoFF = 0x00 1

CpuWriteIoNOP = 0x00 2
CpuWriteIoNOP = 0xE0 1
CpuWriteIoNOP = 0xE8 1

SSIO = io 0x00

# this is "OP4"
# CpuWriteIoNOP = 0x08 1

#CpuLogIoWr = 0x00 0x7
#CpuLogIoWr = 0x08 0x13
#CpuLogIoWr = 0x20 0xBF
#CpuWriteIoNOP = 0xE0 0x1
#CpuLogIoWr = 0xE1 0xE
#CpuLogIoWr = 0xF1 0xE
CpuLogIoRd = 0xE0 0x10

# map CTC chip at 0xF0 - 0xF3
CTCAddr = io 0xF0	

# Dip1 = io 0x03

# 
# Change Log
# ----------
# $Log: MCR3.GAM $
# Revision 1.4  1997/07/04 10:01:34  MCUDDY
# changes for 1.1 Beta 4 
# Revision 1.3  1997/05/13 07:17:12  MCUDDY
# Revision 1.2  1997/04/29 14:18:06  MCUDDY
# Revision 1.1  1997/04/29 06:55:50  MCUDDY
# Initial revision
#